Traditionally, integrated circuits are built upon a flat disk shaped crystal silicon substrate, hereinafter referred to as a blank silicon wafer. The surface of a blank silicon wafer is subdivided into a plurality of rectangular areas on which are formed photolithographic images, such as photolithographic images 15A, 15B, 15C, 15D, 15E, 15F, 15G, 15H, 15I, 15J, 15K, 15L, 15M, 15N and 15P on wafer 13 of FIG. 1. Not all of the photolithographic images in FIG. 1 are numbered for clarity. Commonly, each of the photolithographic images is identical to another photolithographic image on a given wafer, such as wafer 13. Through a series of integrated circuit processing steps, each of the rectangular areas of wafer 13 eventually becomes an individual integrated circuit die.
FIG. 2A illustrates an enlargement of photolithographic image 15A, illustrating a dense electrical wiring area 25 and a small structure wiring area 29 included in photolithographic image 15A. A dense electrical wiring area is any area of a photolithographic image which has a higher density of electrical wiring than other areas and can include, for example, a static random access memory (SRAM) or other random access memory circuit. A small structure wiring area is any of a photolithographic image which has a small quantity of electrical wiring and which is surrounded by an area sparse of electrical wiring, and can include, for example, a single electrical connection line as might be possible in logic circuitry. As each photolithographic image is typically identical to another photolithographic image, the dense electrical wiring area 25 and the small structure wiring area 29 in each of the photolithographic images form a repeating pattern on wafer 13.
Until recently, use of precision polish machines in semiconductor integrated circuit manufacture was restricted to the final preparation of blank silicon wafers, after which the blank silicon wafers were used as substrates for manufacturing the integrated circuits, without any further polishing. Recently, precision polishing has found new uses, subsequent to the final preparation of the blank silicon wafer, during the manufacture of integrated circuits. For instance, U.S. Pat. No. 4,910,155, entitled "Wafer Flood Polishing" granted to Cote et al. issued Mar. 20, 1990, describes a method of polishing wafers during integrated circuit manufacture using polishing pads adapted from pads used in the final preparation of blank silicon wafers, prior to construction of integrated circuits. The pads used in the final preparation were originally designed to polish both sides of a blank silicon wafer (double sided polishing) to a flatness and to a parallelism specification. The new polishing processes used during the manufacture of integrated circuits require only one side of a wafer to be polished, without reference to the other side of the wafer (single sided polishing).
Many of the new polishing processes remove unwanted protrusions formed on the surface of the wafer during some processes associated with integrated circuit manufacture. For example, aluminum wires, formed in a photolithographic image to interconnect transistor junctions, are subsequently coated with an insulation layer, such as silicon dioxide resulting in the unwanted protrusions. The formation of unwanted protrusions is illustrated in a representative cross-section of two portions of a typical integrated circuit die 15A shown in FIG. 2B. Substrate 21, has electrically conductive lines 25A, 25B, 25C, 25D, 25E, 25F, 25G (collectively referred to by reference numeral 25) and 29, typically made of an aluminum alloy. Electrically conductive lines 25 and 29 are then coated with a glass or other insulating layer 20.
As insulating layer 20 is deposited, insulating layer 20 conforms to the existing surface, including lines 25 and 29 to form corresponding protrusions 27A, 27B, 27C, 27D, 27E, 27F, 27G (collectively referred to by reference numeral 27) and 23. Therefore protrusions 27 and 23 are shapes replicated on a wafer surface 24 by insulating layer 20, from the topography below insulating layer 20. Each of the protrusions, such as protrusions 27A, 27B, 27C and 23 has a top surface, such as top surfaces 27AT, 27BT, 27CT, 27GT and 23T which are parallel to wafer surface 24. Not all top surfaces are numbered for clarity. In a typical 0.7 micron CMOS process, before polish, insulation layer 20 has a thickness t1=t2=20,000 .ANG. and protrusions 27 and 23 have a height t4 equal to t3, the thickness of electrically conductive lines 25 and 29, which is about 10,000 .ANG.. The distance t5 between the wafer surface 24 and electrically conductive line 29 after polishing is, ideally about 10,000 .ANG..+-.100 .ANG. and changes according to the density and width of protrusions 27 and 23 and also depends on the polishing process parameters such as the size and hardness of a polishing pad.
In present day integrated circuit technology, as more than one electrically conductive layer is required to carry electrical signals to the underlying transistor junctions of the integrated circuits, protrusions 27 and 23 in insulating layer 20 must be smoothed, or planarized i.e. removed so that wafer surface 24 is a planar surface over all of insulating layer 20. Therefore, using conventional planarization techniques, in one case, one of electrically conductive lines 25 is separated from wafer surface 24 by a distance t5 of about 10,000 .ANG. while the electrically conductive line 29 is separated from wafer surface 24 by a distance t5 of about 7000 .ANG. after polishing in the 0.7 micron CMOS process (above). This variation in distance t5 across the same photolithographic image is due to bending of the polishing pad is called the local polishing removal uniformity. Applicant believes that polishing of photolithographic image 15A by a die sized block also results in a similar variation in local polishing removal uniformity, due to tilting or instability of the block.
To remove protrusions 27 and 23, protrusions 27 and 23 are rubbed against a polishing pad 31 (FIG. 3A) by a sideways motion represented by arrow 33. Polishing pad 31 rests on top surfaces of protrusions 27 and 23. Protrusions 27 are formed over dense wiring area 25 and protrusion 23 is formed over small structure wiring area 29. Protrusion 23 is a single protrusion because small structure wiring area 29 is a single electrical connection line located in a less dense wiring area of the integrated circuit. As protrusion 23 is relatively isolated from other protrusions, top surface 23T of protrusion 23 provides less support for polishing pad 31 than the support collectively provided by the top surfaces of protrusions 27.
In some cases the polishing pad eroding surface 35 is partially constructed with an impregnated abrasive while in other cases a liquid slurry is used to deposit small abrasive particles between eroding surface 35 of polishing pad 31 and the surface of the wafer. As polishing starts, eroding surface 35 contacts and is forced against the top surfaces of protrusions 27 and 23. Moreover, depending on the bulk hardness of eroding surface 35, eroding surface 35 bends or distends into the area sparse of electrical wiring, between protrusions 27 and protrusion 23. Therefore insulating layer 20 over the area of sparse electrical wiring or over a large open space without wiring such as the area around point 30 is also polished as protrusions 27 and 23 are polished.
Also, protrusion 23 is polished at a much faster rate than protrusions 27, because within the area covered by protrusions 27, the average raised area that polishing pad 31 rests on is greater, and thus less actual pressure per unit area is applied during polishing on the top surfaces of protrusions 27 as compared to protrusion 23. Therefore the region of photolithographic image 15A (FIG. 1A) covered by protrusions 27 has the slowest rate of material removal in photolithographic image 15A. Faster removal of insulation layer 20 over a small structure wiring area causes insulation layer 20 below protrusion 23 to thin significantly after protrusion 23 has been sufficiently planarized while the more dense structure of protrusion 27 takes longer to be planarized. In actual practice, the total topography will not be reduced if soft polishing pads are used. Only smoothing of the surface protrusions will occur.
Hard polishing pads do not bend as much as soft polishing pads. Therefore as photolithographic image 5A is planarized, a hard polishing pad does not polish protrusion 23 over small structure wiring area 29 at as much of an accelerated rate as a softer polishing pad. The effect of higher polishing rate of one or more protrusions over a small structure wiring area than the polishing rate of protrusions over a dense electrical wiring area results in nonuniform thickness removal and hence nonuniformity of the remaining insulation layer across a photolithographic image, which was described above as local polishing removal uniformity.
FIG. 3B is a cross-sectional view of wafer 13 along the direction 3B--3B of FIG. 1. The protrusions of wafer 13 (FIG. 1) are not visible on wafer 13 (FIG. 3B) and are shown in FIG. 3B as the enlarged insets 37 and 32. In FIG. 3B, polishing pad 31 is typically larger than wafer 13 and touches wafer surface 24 with more pressure at the beginning of polishing in the portion 38 than in the portion 34 because wafer 13 has a curvature. The curvature can be in the form of a potato chip which in cross-section appears as an "S" shaped bow to wafer surface 24 (FIG. 3B), representative of the warpage often found across silicon wafers that have undergone high temperature processing and deposition of many stacked thin film layers on the frontside and backside of wafer 13. Additionally variations in actual wafer thickness causes variations in polishing rate across a wafer.
Curvature of polishing pad 31 deviates from the curvature of wafer 13, depending on the hardness of eroding surface 35. Therefore, polishing pad 31 does not exert a uniform force on wafer 13, unless polishing pad 31 is soft enough to completely conform to wafer surface 24 of a warped wafer 13. In FIG. 3B, the height of protrusions on wafer surface 24 in portion 38 (cross-section 37) is smaller than the height of the protrusions on wafer surface 24 in portion 34 (cross-section 32) because of difference in polishing pressure. The polishing pressure difference across the whole eroding surface of a polishing pad leads to nonuniform removal and hence nonuniform thickness of the remaining insulation layer, because polishing has to continue after the protrusions are removed in portion 38 until all protrusions are removed in portion 34. Such nonuniformity of the insulation layer remaining after polishing across a large part of a wafer is hereinafter referred to as global polishing removal uniformity.
Workers in the art of polishing semiconductor wafers for the purpose of integrated circuit planarization have found that a soft polishing pad achieves good global polishing removal uniformity but poor local polishing uniformity. In contrast, a hard polishing pad achieves good local polishing removal uniformity but poor global polishing removal uniformity.
To achieve both good local polishing removal uniformity and good global polishing removal uniformity during the same polishing process, many workers in the field have experimented with layered polishing pads. U.S. Pat. No. 5,257,478 entitled "Apparatus for Interlayer Planarization of Semiconductor Material" by Hyde and Roberts issued Nov. 2, 1993 describes a pad of "at least two layers" where one layer is harder or less flexible than the other layer. U.S. Pat. No. 5,197,999 entitled "Polishing Pad for Planarization" by Thomas issued Mar. 30, 1993 describes a stiffening agent included in the polishing pad to improve planarization of an integrated circuit. However, significant global polishing removal uniformity is sacrificed when the polishing pad is stiffened to improve local polishing removal uniformity, because a hard pad does not conform to the curvature of a wafer.
To improve local polishing removal uniformity without a significant sacrifice in global polishing removal uniformity, many new polishing pad designs have been recently disclosed. For example, FIG. 3 of "A New Pad and Equipment Development for ILD Planarization" by Beppu et al., Semiconductor World, January 1994 shows use of small polishing blocks suspended on a resilient backing whereby the blocks slide independently across the wafer. Although Beppu et al. fail to explicitly state any dimensions for the blocks, the blocks appear to be twice the size of a protrusion, and hence less than the size of a die. Blocks of such a small size result in loss of local polishing removal uniformity because polish rate is a function of protrusion density.
U.S. Pat. No. 5,212,910 entitled "Composite Polishing Pad for Semiconductor Process" by Breivogel et al. issued May 25, 1993 describes use of a soft backing film behind a hard outer polishing layer. The inner soft layer is divided into tiles (Col. 4, lines 52-68) to give the outer layer more independent resiliency. The lateral dimension of the tiles is optimally selected to correspond approximately to the width of an individual die on the silicon wafer (Col. 5, lines 49-51). However, a die sized tile fails to protect a small structure wiring area from higher polishing rate, because the tile must rest on a corner of a dense electrical wiring area, and on the small structure wiring as shown in FIG. 2A, As polishing progresses, the polishing pad will polish the protrusions over the small structure wiring area faster, causing the tile to tilt.
Such a tilt causes slower polishing of the dense electrical wiring area and faster polishing of the small structure wiring area. Tilt of a block or tile can also cause surface fracturing of the insulating glass and thus failure of the insulation layer. Tilt of a block or tile also results in rounding at the edge of a dense electrical wiring area such as a SRAM.
U.S. Pat. No. 5,230,184 entitled "Distributed Polishing Head" by Bukhman issued Jul. 27, 1993 discloses polishing pads larger than a scribe grid and "usually sized on an order of the individual VLSI die" (Col. 2, lines 64-66). One problem with the apparatus of Bukhman is that when one of the blocks is lifted by a protrusion, the membrane supporting the blocks must lift adjacent blocks by a given amount, and therefore tilt the adjacent blocks, and so reduce the polish rate and removal uniformity of the adjacent blocks. Moreover, a block will tilt as the block leaves a dense electrical wiring area, because the block has the size of a single integrated circuit die. Problems due to tilt of a block have been described above, in reference to Breivogel et al.